Integrated circuits of a semiconductor chip are connected to external circuitry through contacts on a surface of the chip. Typically, the contacts on the chip are disposed in rows extending parallel to and adjacent one or more edges on the active surface of the chip. The semiconductor chip is connected to a substrate that physically supports the chip. The substrate also provides electrical contacts that can be electrically connected to the contacts of the semiconductor chip. The substrate can be made part of a discrete chip package wherein the substrate supports a single chip and provides terminals for connecting to external circuit elements or, alternatively, in a so-called "hybrid circuit," one or more chips are mounted on a single substrate. In the hybrid approach the substrate not only physically supports the chip(s) but also functions as a circuit panel for interconnecting the chip(s) to other electrical components also mounted on the single substrate. In either case, the contacts of the chip must be connected to the contacts of the substrate. Traditionally, there have been four widely used interconnection methods: wire bonding, tape-automated bonding (or "TAB"), flip-chip bonding and beam lead bonding.
In wire bonding, the substrate has a top surface with a plurality of electrically conductive contact pads. The semiconductor chip has a face surface (i.e., the surface that bears the chip contacts) and a back surface. The chip is secured to the top surface of the substrate such that the back surface of the chip contacts with the top surface of the substrate and the substrate contacts surround the chip perimeter. Fine wires are then connected between the semiconductor contacts and the substrate contacts.
The tape automated bonding method uses a dielectric supporting tape, such as a thin film of polyimide having a hole slightly larger than the chip. An array of metallic leads is provided on one surface of the dielectric layer. These leads extend inwardly from around the hole toward the edges of the hole. Each lead has an innermost end projecting inwardly, beyond the edge of the hole. The innermost ends of the leads are arranged side by side at a spacing corresponding to the spacing of the contacts on the chip. The dielectric film is juxtaposed with the chip so that the hole is aligned with the chip and so that the innermost ends of the leads will extend over the front or contact bearing surface of the chip. The innermost ends of the leads are then bonded to the contacts of the chip, as by ultrasonic or thermocompression bonding. The outer ends of the leads are connected to external circuitry.
In flip-chip bonding, contacts on the front surface of the chip are provided with bumps of solder. The substrate has contacts arranged in an array corresponding to the array of contacts on the chip. The chip, with the solder bumps, is inverted so that its front surface faces towards the top surface of the substrate, with each contact and solder bump on the chip being positioned on the appropriate contact of the substrate. The assembly is then heated so as to liquefy the solder and bond each contact on the chip to the confronting contact of the substrate.
In a "beam lead" process, the chip is provided with individual leads extending from contacts on the front surface of the chip outwardly beyond the edges of the chip. The chip is positioned on a substrate with the outermost ends of the individual leads protruding over contacts on the substrate. The leads are then engaged with the contacts and bonded thereto so as to connect the contacts on the chip with contacts on the substrate.
Recent improvements in semiconductor interconnection methods can be found, for example, in commonly assigned U.S. Pat. Nos. 5,148,265 and 5,148,266 entitled "Semiconductor Chip Assemblies With Fan-In Leads" and "Semiconductor Chip Assemblies Having Interposer and Flexible Lead" respectively, the text of both such patents incorporated herein by reference. In part, the '265 and '266 patents disclose a semiconductor chip assembly method using an interposer. The interposer has a top surface with conductive terminals and a bottom surface. The interposer is laid over the central portion of the contact-bearing surface of the semiconductor chip such that the bottom surface of the interposer contacts the chip's contact-bearing surface and the peripheral contacts of the semiconductor chip are exposed. Contact leads are then interconnected between the semiconductor contacts and the terminals on the interposer. The terminals on the interposer are typically disposed in an area array. The interposer may also be provided with a compliant layer disposed between the terminals and the chip. Such a compliant layer permits slight vertical movement of the terminals toward the chip during testing and further absorb stresses applied to the leads thus improving the reliability of the interconnect.
Further improvements are described in commonly assigned U.S. Pat. No. 5,398,863 entitled "Shaped Lead Structure and Method" and commonly assigned U.S. Pat. No. 5,491,302 entitled "Microelectronic Bonding With Lead Motion."
In part, the '863 patent discusses the desirability of obtaining "s-shaped" bond ribbons that connect between the contacts of a support structure of the connection component and the contacts of the semiconductor chip. S-shaped bond ribbons are more reliable than kinked bond ribbons since they can better absorb forces directed at the bond ribbon due. However, while the '863 patent describes how the horizontal motion of the bonding tool can be controlled so as to obtain a better s-shaped bond ribbon, it does not disclose how design of the bond ribbon itself can facilitate the formation of the desired s-shaped bond ribbon. In part, U.S. Pat. No. 5,491,302 discloses how a single tapered section can be formed to approximate a beam of uniform strength in bending with respect to vertical forces applied by a bonding tool.
Despite the positive results of the aforementioned commonly owned inventions, still further improvements would be desirable.